T6J05 2001-11-29 1 toshiba cmos digital integrated circuit silicon monolithic T6J05 row driver for a dot matrix lcd the T6J05 is a 128-channel-output row driver for an stn dot matrix lcd. the T6J05 features an 80-v lcd drive voltage. the T6J05 is able to drive lcd panels with a duty ratio of up to 1/480. it is recommended for use with the t6c71. features display duty application : to 1/480 lcd drive signal : 128 data transfer : 128-bit bidirectional (1) o1 o128 (2) o128 o1 lcd drive voltage : v cc = 18.5 to 42.5 v, v m = 2.5 v, v ee = ? 13.5 to ? 37.5 v power supply voltage : 2.7 to 5.5 v operating temperature : ? 20 to 75c lcd drive output resistance : 0.6 k ? (typ.) (v cc = v h = 32.5 v, v ee = v l = ? 27.5 v) display-off function : when/dspof is l, all lcd drive outputs (o1 to o128) remain at the v m level. lcd drive output timing : change on falling edge of lp blanking function : provision of a blanking interval prevents excessively high voltages being applied to the electrodes of the liquid crystal panel. /blnk = l : blanking. all lcd drive outputs (o1 to o128) are set to the v m level. /blnk = h: (o1 to o128) are operational. please contact toshiba or an authorized toshiba dealer for information on package dimensions. tcp (tape carrier package) unit: mm lead pitch 0.8 in (uam, 3ns) out (ubm, 3ns) (udn, 3ns) 0.8 0.8 0.20 0.24 0.18 T6J05
T6J05 2001-11-29 2 block diagram pin assignment note: the above diagram shows the pin configuration of the lsi chip, not that of the tape carrier package. it short-circuits v l l and v ee l/v h l and v cc l on the chip.
T6J05 2001-11-29 3 pin functions pin name i / o functions level o1 to o128 output output for lcd drive signal v h / v m / v l dio1, dio2 i / o input / output for shift data dir = l : dio1 is input, dio2 is output dir = h: dio1 is output, dio2 is input lp input (shift clock pulse) input for shift clock pulse fr input (frame) input for frame signal dir input (direction) input for data flow direction select / dspof input (display off) / dspof = l: display ? off mode, (o1 to o128) remain at the v m level. latch outputs cleared after release / dspof = h: display ? on mode, (o1 to o128) are operational / blnk input (blanking function) blanking ? off mode. (o1 to o128) remain at v m level. latch outputs not cleared blanking ? on mode. (o1 to o128) are operational test input (test) fix to l v dd to v ss v dd D power supply for internal logic (5 v) v ss D power supply for internal logic (0 v) v h l / r v cc l / r D power supply for lcd drive circuit v m l / r D power supply for lcd drive circuit v l l / r v ee l / r D power supply for lcd drive circuit D relation between fr, data input and output level format f r data input / dspof or / blnk output level l l h v m l h h v h h l h v m h h h v l * * l v m *: don?t care data input format data input terminals dual data flow dio1 dio2 l o1 o128 in out h o128 o1 out in
T6J05 2001-11-29 4 ti m i ng di agram 1
T6J05 2001-11-29 5 timing diagram 2 (blanking function)
T6J05 2001-11-29 6 absolute maximum ratings (ensure that the following conditions are maintained, v cc v h v dd v m v ss v l v ee ) (note 1) item symbol pin name rating unit supply voltage 1 v dd v dd ? 0.3 to 7.0 v v cc ? v ee v cc l / r, v ee l / r ? 0.3 to 85 supply voltage 2 v h ? v ee v h l / r, v ee l / r ? 0.3 to 85 v supply voltage 3 v m ? v ee v m l / r, v ee l / r ? 0.3 to 85 v supply voltage 4 v l ? v ee v l l / r, v ee l / r ? 0.3 to 85 v input voltage v in (note 2) ? 0.3 to v dd + 0.3 v operating temperature t opr D ? 20 to 75 c storage temperature t stg D ? 40 to 125 c note 1: input voltage: v ss v dd v ee / v l v cc / v h v m note 2: lp, fr, dir, dual, dio1, dio2, dmin, / dspof, / blnk, test electrical characteristics dc characteristics (unless otherwise noted, v ss = 0 v, v dd = 2.7 to 5.5 v, ta = ? 20 to 75c) (ensure that the following conditions are maintained, v cc v h v dd v m v ss v l v ee ) item symbol test circuit test condition min typ. max unit pin name supply voltage 1 v dd D D 2.7 5.0 5.5 v v dd supply voltage 2 v cc ? v m v m ? v ee D D 16 D 40 v v cc l / r v ee l / r h level v ih (note 3) 0.6 v dd D v dd input voltage l level v il D (note 3) 0 D 0.2 v dd v (note 2) h level v oh i oh = ? 0.5 ma v dd ? 0.5 D v dd output voltage l level v ol D i ol = 0.5 ma 0 D 0.5 v dio1 dio2 h level r oh v out = v h ? 0.5 v (note 4) D 0.6 1.2 r om v out = v m + 0.5 v (note 4) D 0.6 1.2 m level r om v out = v m ? 0.5 v (note 4) D 0.6 1.2 output resistance l level r ol D v out = v l + 0.5 v (note 4) D 0.6 1.2 k ? o1 to o128 v dd = 5.5 v D D 60 i ss ope v dd = 2.7 v function (note 5) D D 30 v dd v dd = 5.5 v D D 200 i cc ope v dd = 2.7 v function (note 5) D D 200 v cc l / r current consumption i cc leak D v dd = 5.5 v v cc ? v ee = 80 v standby ? 10 D 10 a v cc l / r note 3: v dd = 4.5 to 5.5 v, v dd = 2.7 v: v ih = 0.7 v dd (min), v il = 0.2 v dd (max) note 4: v dd = 2.7 v, v h = 32.5 v, v m = 2.5 v, v l = ? 27.5 v note 5: no load, f lp = 48 khz, f fr = 2.4 khz, f dio = 400 hz, v ih = v dd , v il = v ss
T6J05 2001-11-29 7 ac characteristics test conditions (1) (v dd = 4.5 to 5.5 v) item symbol test condition min max unit lp pulse width h t cwh lp 30 D ns lp pulse width l t cwl lp 195 D ns input rise / fall time t r , t f lp, fr, dio1, dio2 D 50 ns data set ? up time t dsu dio1, dio2 30 D ns data hold time t dhd dio1, dio2 30 D ns output data delay time (note 6) t pd dio1, dio2 40 150 ns lcd drive data delay time (note 7) t hpd o1 to o128 D 1.0 s note 6: c l = 30 pf note 7: no load, v ss = 0 v, v m = 2.5 v, v h = 42.5 v, v l = ? 37.5 v test conditions (2) (v dd = 2.7 to 4.5 v) item symbol test condition min max unit lp pulse width h t cwh lp 100 D ns lp pulse width l t cwl lp 400 D ns input rise / fall time t r , t f lp, fr, dio1, dio2 D 50 ns data set ? up time t dsu dio1, dio2 60 D ns data hold time t dhd dio1, dio2 30 D ns output data delay time (note 8) t pd dio1, dio2 40 400 ns lcd drive data delay time (note 9) t hpd o1 to o128 D 1.2 s note 8: c l = 30 pf note 9: no load, v ss = 0 v, v m = 2.5 v, v h = 42.5 v, v l = ? 37.5 v
T6J05 2001-11-29 8 handling precautions insert the bypass capacitor (0.1 f) between v dd and v ss to decrease power supply noise. position the bypass capacitor as close to the lsi as possible. set/dspdf to l at power on so as to protect power supply ic. pay attention to measure and treatment of latch-up because being high-withstand pressure product.
T6J05 2001-11-29 9 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. polyimide base film is hard and thin. be careful not to injure yourself on the film or to scratch any other parts with the film. try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. when cutting out the film, try to ensure that the film shavings do not cause accidents. after use, treat the leftover film and reel spacers as industrial waste. light striking a semiconductor device generates electromotive force due to photoelectric effects. in some cases this can cause the device to malfunction. this is especially true for devices in which the surface (back), or side of the chip is exposed. when designing circuits, make sure that devices are protected against incident light from external sources. exposure to light both during regular operation and during inspection must be taken into account. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707ebe restrictions on product use
|
